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november 1991 order number: 290256-001 8742 universal peripheral interface 8-bit slave microcontroller y 8742: 12 mhz y pin, software and architecturally compatible with 8741a y 8-bit cpu plus rom, ram, i/o, timer and clock in a single package y 2048x8eprom,128x8 ram, 8-bit timer/counter, 18 programmable i/o pins y one 8-bit status and two data registers for asynchronous slave-to- master interface y dma, interrupt, or polled operation supported y fully compatible with all intel and most other microprocessor families y expandable i/o y ram power-down capability y over 90 instructions: 70% single byte y available in express e standard temperature range the intel 8742 is a general-purpose universal peripheral interface that allows designers to grow their own customized solution for peripheral device control. it contains a low-cost microcomputer with 2k of program memory, 128 bytes of data memory, 8-bit timer/counter, and clock generator in a single 40-pin package. interface registers are included to enable the upi device to function as a peripheral controller in the mcs -48, mcs-51, mcs-80, mcs-85, 8088, 8086 and other 8-, 16-bit systems. the 8742 is software, pin, and architecturally compatible with the 8741a. the 8742 doubles the on-chip memory space to allow for additional features and performance to be incorporated in upgraded 8741a de- signs. for new designs, the additional memory and performance of the 8742 extends the upi concept to more complex motor control tasks, 80-column printers and process control applications as examples. 290256 2 figure 1. pin configuration 1
8742 290256 1 figure 2. block diagram 2 2
8742 table 1. pin description dip symbol pin type name and function no. test 0, 1 i test inputs: input pins which can be directly tested using conditional branch instructions. test 1 39 frequency reference: test 1 (t 1 ) also functions as the event timer input (under software control). test 0 (t 0 ) is used during prom programming and eprom verification. xtal 1, 2 i inputs: inputs for a crystal, lc or an external timing signal to determine the internal oscillator frequency. xtal 2 3 reset 4i reset: input used to reset status flip-flops and to set the program counter to zero. reset is also used during eprom programming and verification. ss 5i single step: single step input used in conjunction with the sync output to step the program through each instruction (eprom). this should be tied to a 5v when not used. cs 6i chip select: chip select input used to select one upi microcomputer out of several connected to a common data bus. ea 7 i external access: external access input which allows emulation, testing and eprom verification. this pin should be tied low if unused. rd 8i read: i/o read input which enables the master cpu to read data and status words from the output data bus buffer or status register. a 0 9i command/data select: address input used by the master processor to indicate whether byte transfer is data (a 0 e 0, f1 is reset) or command (a 0 e 1, f1 is set). a 0 e 0 during program and verify operations. wr 10 i write: i/o write input which enables the master cpu to write data and command words to the upi input data bus buffer. sync 11 o output clock: output signal which occurs once per upi instruction cycle. sync can be used as a strobe for external circuitry; it is also used to synchronize single step operation. (bus) d 0 d 7 12 19 i/o data bus: three-state, bidirectional data bus buffer lines used to interface the upi microcomputer to an 8-bit master system data bus. p 10 p 17 27 34 i/o port 1: 8-bit, port 1 quasi-bidirectional i/o lines. p 20 p 27 21 24 i/o port 2: 8-bit, port 2 quasi-bidirectional i/o lines. the lower 4 bits (p 20 p 23 ) interface directly to the 8243 i/o expander device and contain address and data information during 3538 port 4 7 access. the upper 4 bits (p 24 p 27 ) can be programmed to provide interrupt request and dma handshake capability. software control can configure p 24 as output buffer full (obf) interrupt, p 25 as input buffer full (ibf ) interrupt, p 26 as dma request (drq), and p 27 as dma acknowledge (dack ). prog 25 i/o program: multifunction pin used as the program pulse input during prom programming. during i/o expander access the prog pin acts as an address/data strobe to the 8243. this pin should be tied high if unused. v cc 40 power: a 5v main power supply pin. v dd 26 power: a 5v during normal operation. a 21v during programming operation. low power standby supply pin. v ss 20 ground: circuit ground potential. 3 3
8742 upi-42 features 1. two data bus buffers, one for input and one for output. this allows a much cleaner master/slave protocol. 290256 3 2. 8 bits of status st 7 st 6 st 5 st 4 f 1 f 0 ibf obf d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 st 4 st 7 are user definable status bits. these bits are defined by the ``mov sts, a'' single byte, single cycle instruction. bits 4 7 of the acccumu- lator are moved to bits 4 7 of the status register. bits 0 3 of the status register are not affected. mov sts, a op code: 90h 1 001000 0 d 7 d 0 3. rd and wr are edge triggered. ibf, obf, f 1 and int change internally after the trailing edge of rd or wr . 290256 4 during the time that the host cpu is reading the status register, the 8742 is prevented from updat- ing this register or is ``locked out''. 4. p 24 and p 25 are port pins or buffer flag pins which can be used to interrupt a master proces- sor. these pins default to port pins on reset. if the ``en flags'' instruction has been execut- ed, p 24 becomes the obf (output buffer full) pin. a ``1'' written to p 24 enables the obf pin (the pin outputs the obf status bit). a ``0'' written to p 24 disables the obf pin (the pin remains low). this pin can be used to indicate that valid data is avail- able from the upi-41a (in output data bus buff- er). if ``en flags'' has been executed, p 25 becomes the ibf (input buffer full) pin. a ``1'' written to p 25 enables the ibf pin (the pin outputs the inverse of the ibf status bit. a ``0'' written to p 25 disables the ibf pin (the pin remains low). this pin can be used to indicate that the upi is ready for data. 290256 5 data bus buffer interrupt capability en flags op code: 0f5h 1 111010 1 d 7 d 0 5. p 26 and p 27 are port pins or dma handshake pins for use with a dma controller. these pins default to port pins on reset. if the ``en dma'' instruction has been executed, p 26 becomes the drq (dma request) pin. a ``1'' written to p 26 causes a dma request (drq is acti- vated). drq is deactivated by dack # rd, dack # wr, or execution of the ``en dma'' in- struction. if ``en dma'' has been executed, p 27 becomes the dack (dma acknowledge) pin. this pin acts as a chip select input for the data bus buffer reg- isters during dma transfers. 290256 6 dma handshake capability en dma op code: 0e5h 1 110010 1 d 7 d 0 6. the reset input on the 8742, includes a 2-stage synchronizer to support reliable reset operation for 12 mhz operation. 7. when ea is enabled on the 8742, the program counter is placed on port 1 and the lower three bits of port 2 (msb e p 22 , lsb e p 10 ). on the 8742 this information is multiplexed with port data (see port timing diagrams at end of this data sheet). 4 4
8742 applications 290256 7 figure 3. 8088-8742 interface 290256 9 figure 5. 8742-8243 keyboard scanner 290256 8 figure 4. 8048h-8742 interface 290256 10 figure 6. 8742 80-column matrix printer interface 5 5
8742 programming, verifying, and erasing the 8742 eprom programming verification in brief, the programming process consists of: acti- vating the program mode, applying an address, latching the address, applying data, and applying a programming pulse. each word is programmed com- pletely before moving on to the next and is followed by a verification step. the following is a list of the pins used for programming and a description of their functions: pin function xtal 1 clock-input reset initialization and address latching test 0 selection of program or verify mode ea activation of program/verify modes bus address and data input data output during verify p 2012 address input v dd programming power supply prog program pulse input warning an attempt to program a missocketed 8742 will result in severe dam- age to the part. an indication of a properly socketed part is the ap- pearance of the sync clock output. the lack of this clock may be used to disable the programmer. the program/verify sequence is: 1. a 0 e 0v, cs e 5v, ea e 5v, reset e 0v, testo e 5v, v dd e 5v, clock applied or inter- nal oscillator operating, bus floating, prog e 5v. 2. insert 8742 in programming socket 3. test 0 e 0v (select program mode) 4. ea e 18v (active program mode) 5. address applied to bus and p 2022 6. reset e 5v (latch address) 7. data applied to bus ** 8. v dd e 21v (programming power) 9. prog e v cc followed by one 50 ms pulse to 18v 10. v dd e 5v 11.test 0 e 5v (verify mode) 12. read and verify data on bus 13. test 0 e 0v 14. reset e 0v and repeat from step 5 15. programmer should be at conditions of step 1 when 8742 is removed from socket 8742 erasure characteristics the erasure characteristics of the 8742 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 angstroms ( e ). it should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000 e range. data shows that constant exposure to room level fluorescent lighting could erase the typical 8742 in approximately 3 years while it would take approximately one week to cause erasure when exposed to direct sunlight. if the 8742 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from intel which should be placed over the 8742 window to prevent unintentional erasure. the recommended erasure procedure for the 8742 is exposure to shortwave ultraviolet light which has a wavelength of 2537 e . the integrated dose (i.e., uv intensity c exposure time) for erasure should be a minimum of 15 w-sec/cm 2 . the erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 m w/cm 2 power rat- ing. the 8742 should be placed within one inch of the lamp tubes during erasure. some lamps have a filter on their tubes which should be removed before erasure. 6 6
8742 absolute maximum ratings * ambient temperature under bias 0 cto70 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 0.5 to a 7v power dissipation1.5w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. d.c. characteristics t a e 0 to a 70 c, v cc e v dd ea 5v g 10% symbol parameter 8742 units test min max conditions v il input low voltage (except xtal1, xtal2, reset) b 0.5 0.8 v v il1 input low voltage (xtal1, xtal2, reset) b 0.5 0.6 v v ih input high voltage (except xtal1, xtal2, reset) 2.0 v cc v v ih1 input high voltage (xtla1, xtal2, reset) 3.5 v cc v v ol output low voltage (d 0 d 7 ) 0.45 v i ol e 2.0 ma v ol1 output low voltage (p 10 p 17 ,p 20 p 27 , sync) 0.45 v i ol e 1.6 ma v ol2 output low voltage (prog) 0.45 v i ol e 1.0 ma v oh output high voltage (d 0 d 7 ) 2.4 v i oh eb 400 m a v oh1 output high voltage (all other outupts) 2.4 i oh eb 50 m a i il input leakage current (t 0 ,t 1 , rd, wr, cs, a 0 , ea) g 10 m av ss s v in s v cc i ofl output leakage current (d 0 d 7 , high z state) g 10 m a v ss a 0.45 s v out s v cc i li low input load current (p 10 p 17 ,p 20 p 27 ) 0.3 ma v il e 0.8v i li1 low input load current (reset, ss) 0.2 ma v il e 0.8v i dd v dd supply current 10 ma typical e 5ma i cc a i dd total supply current 125 ma typical e 60 ma i ih input leakage current (p 10 p 17 ,p 20 p 27 ) 100 m av in e v cc c in input capacitance 10 pf c 10 i/o capacitance 20 pf d.c. characteristicseprogramming t a e 25 c g 5 c, v cc e 5v g 5%, v dd e 21v g 0.5v symbol parameter min max units test conditions v doh v dd program voltage high level 20.5 21.5 v v ddl v dd voltage low level 4.75 5.25 v v ph prog program voltage high level 17.5 18.5 v v pl prog voltage low level v cc b 0.5 v cc v v eah ea program or verify voltage high level 17.5 18.5 v v eal ea voltage low level 5.25 v i dd v dd high voltage supply current 30.0 ma i prog prog high voltage supply current 1.0 ma i ea ea high voltage supply current 1.0 ma 7 7
8742 a.c. characteristics t a e 0 cto a 70 c, v ss e 0v, v cc e v dd ea 5v g 10% dbb read symbol parameter 8742 units min max t ar cs, a 0 setup to rd v 0ns t ra cs, a 0 hold after rd u 0ns t rr rd pulse width 160 ns t ad cs, a 0 to data out delay 130 ns t rd rd v to data out delay 130 ns t df rd u to data float delay 85 ns t cy cycle time 1.25 15 m s (1) dbb write symbol parameter min max units t aw cs, a 0 setup to wr v 0ns t wa cs, a 0 hold after wr u 0ns t ww wr pulse width 160 ns t dw data setup to wr u 130 ns t wd data hold after wr u 0ns note: 1. t cy e 15/f(xtal) a.c. characteristics t a e 25 c g 5 c, v cc e 5v g 5%, v dd ea 21v g 0.5 programming symbol parameter min max units test conditions t aw address setup time to reset u 4t cy t wa address hold time after reset u 4t cy t dw data in setup time to prog u 4t cy t wd data in hold time after prog v 4t cy t ph reset hold time to verify 4t cy t vddw v dd setup time to prog u 0 1.0 ms t vddh v dd hold time after prog u 0 1.0 ms t pw program pulse width 50 60 ms t tw test 0 setup time for program mode 4t cy t wt test 0 hold time after program mode 4t cy t do test 0 to data out delay 4t cy t ww reset pulse width to latch address 4t cy t r ,t f v dd and prog rise and fall times 0.5 2.0 m s t cy cpu operation cycle time 4.0 m s t re reset setup time before ea u 4t cy note: if test 0 is high, t do can be triggered by reset u . 8 8
8742 a.c. characteristics dma symbol parameter 8642/8742 units min max t acc dack to wr or rd 0 ns t cac rd or wr to dack 0 ns t acd dack to data valid 130 ns t crq rd or wr to drq cleared 100 ns (1) note: 1. c l e 150 pf. a.c. characteristics port 2 t a e 0 cto a 70 c, v cc ea 5v g 10% symbol parameter f(t cy ) 8742/8642 (3) units min max t cp port control setup before falling edge of prog 1/15 t cy b 28 55 ns (1) t pc port control hold after falling edge of prog 1/10 t cy 125 ns (2) t pr prog to time p2 input must be valid 8/15 t cy b 16 650 ns (1) t pf input data hold time 0 150 ns (2) t dp output data setup time 2/10 t cy 250 ns (1) t pd output data hold time 1/10 t cy b 80 45 ns (2) t pp prog pulse width 6/10 t cy 750 ns notes: 1. c l e 80 pf. 2. c l e 20 pf. 3. t cy e 1.25 m s. a.c. testing input/output waveform input/output 290256 11 a.c. testing load circuit 290256 12 crystal oscillator mode 290256 13 crystal series resistance should be k 750 at 12 mhz; k 180 x at 3.6 mhz. driving from external source 290256 14 rise and fall times should not exceed 20 ns. resis- tors to v cc are needed to ensure v ih e 3.5v if ttl circuitry is used. 9 9
8742 lc oscillator mode f e 1 2 q 0 lc l c nominal 45 h 20 pf 5.2 mhz c e c a 3cpp 2 120 h 20 pf 3.2 mhz cpp j 5pf10pf pin-to-pin capacitance 290256 15 each c should be approximately 20 pf, including stray capacitance. waveforms read operationedata bus buffer register 290256 16 write operationedata bus buffer register 290256 17 clock timing 290256 23 10 10
8742 waveforms combination program/verify mode 290256 18 verify mode 290256 19 notes: 1. prog must float if ea is low or ea is low or if test 0 e 5v. 2. a 0 must be held low (i.e., e 0v) during program/verify modes. 3. test 0 must be held high. the 8742 eprom can be programmed by the fol- lowing intel products: 1. universal prom programmer (upp 103) periph- eral of the intellec development system with a upp-549 personality card. 2. iup-200/iup-201 prom programmer with the iup-f87/44 personality module. 11 11
8742 waveforms (continued) dma 290256 20 port 2 290256 21 port timing during external access (ea) 290256 22 on the rising edge of sync and ea is enabled, port data is valid and can be strobed on the trailing edge of sync the program counter contents are available. 12 12

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